The present invention relates to a DSP (Digital Signal Processor) control apparatus and method and, more particularly, to a DSP control apparatus and method capable of reducing DSP power consumption.
In information equipment and communications equipment such as a CDMA (Code Division Multiple Access) radio terminal, a DSP is generally arranged in addition to a CPU (Central Processing Unit) for controlling the entire equipment. The DSP performs various signal processing operations so as to cope with high-density, high-speed signal processing or an increase in digital signal processing amount.
A DSP of this type is controlled on the basis of event-driven processing. The DSP is normally set in an idle state. The DSP is started by an interrupt when a controller issues a task. The DSP performs desired digital signal arithmetic processing. The DSP returns to the idle state upon completing the arithmetic processing.
The maximum required arithmetic processing amount of a system in a frame having a predetermined period of time is conventionally predicted, as shown in FIG. 10. The clock frequency is generally so fixed as to always complete the arithmetic processing amount for each frame within a frame. The clock frequency must be set to obtain a margin of an idle time tml and not to make an arithmetic processing time tsl short.
No problem occurs in this conventional DSP control apparatus when the arithmetic processing amount of the DSP is always constant. When the arithmetic processing amount greatly changes, e.g., when the arithmetic processing amount becomes extremely small in a time interval T2 shown in FIG. 10, an arithmetic processing time ts2 is shortened to prolong an idle time tm2 under the condition that an arithmetic processing rate S is constant. As a result, the power is wastefully consumed.
In the idle state, the clock supplied to the DSP may be disabled to reduce the current consumption in the DSP on the average. To disable the clock supplied to the DSP, an external oscillator circuit must be temporarily stopped. When the oscillator circuit resumes oscillation, a time (nonnegligible time length) is required to stabilize oscillation. When an event is driven to supply an interrupt to the DSP, arithmetic processing cannot be immediately started.
Even in the idle state, the external oscillator circuit for supplying clocks to the DSP must be kept continued, and the power consumption of the external oscillator circuit cannot be set zero. For example, when the idle state per unit time is long due to a small DSP processing amount, the power consumption cannot be reduced in proportion to the processing amount.
A clock having a relatively low frequency may be supplied to the DSP in order to reduce the time interval of the idle state. In this case, a maximum arithmetic processing amount in full-operation of the DSP is undesirably reduced.
It is an object of the present invention to provide a DSP control apparatus capable of reducing the power consumption of a DSP and its peripheral circuits.
In order to achieve the above object of the present invention, there is provided a digital signal processor (DSP) control apparatus comprising arithmetic processing means for performing digital signal arithmetic processing using a clock having a variable frequency, estimation means for estimating an arithmetic processing amount of the arithmetic processing means, calculation means for calculating a new clock frequency on the basis of an estimated arithmetic processing amount from the estimation means, and clock supply means for supplying a clock having a frequency calculated by the calculation means to the arithmetic processing means.